1. Field of the Invention
The invention generally relates to a power supply voltage switching circuit, and more particularly, to a power supply voltage switching circuit having a high voltage selecting module.
2. Description of the Prior Art
In certain application of IC technology, situations might occur where a different power supply voltage is required for operating in different modes, such as non-volatile flash memory. In prior art, a power supply voltage switch circuit is often used to accomplish the switching of different power supply voltages in different operating modes.
Please refer to FIG. 1, which shows a schematic diagram of a conventional power supply voltage switching circuit 10 according to prior art. The power supply voltage switching circuit 10 comprises a level shifting module 12 for shifting the level of the input signal to a comparatively high level before outputting the signal. In FIG. 1, the level shifting module 12 comprises two level-shifters 14 and 16 for respectively shifting levels of the two input signals, wherein the voltage level of the comparatively high level signal after level shifting is determined by the power supply voltage of the level-shifters 14 and 16. The power supply voltage switching circuit 10 further comprises a selecting switch module 18, where the selecting switch module 18 in FIG. 1 is made up of a first p-type MOS transistor 20 and a second p-type MOS transistor 22. The selecting switch module 18 selects from either a first voltage VPP or a second voltage VDD to generate a power supply voltage VPS for an integrated circuit according to the comparatively high level signals generated by the level shifting module 12.
In the actual application, the level of the first voltage VPP is usually the level after charge pumping such as 7V˜0V and the second voltage VDD is usually the standard voltage used in common integrated circuits such as 3V˜0V. Therefore, generally speaking, if the integrated circuit wishes to operate at a different voltage mode, a control circuit (not shown in FIG. 1) generates a first control signal ENVPP to control the power supply voltage switching circuit 10 in generating the desired power supply voltage VPS. In FIG. 1, besides the first control signal ENVPP, the control circuit can also generate a second control signal ENVDD which is a complementary signal of the first control signal ENVPP, for controlling the power supply voltage switching circuit 10. The power supply voltage of the control circuit is the standard voltage so the level of both the first control signal ENVPP and the second control signal ENVDD is within the standard range (3V˜0V).
As previously mentioned, the level of the shifted comparatively high level signal from the level shifting module 12 corresponds to the power supply voltage of the level-shifters 14 and 16. In FIG. 1, the power supply voltage of the level-shifters 14 and 16 is the first voltage VPP, therefore the level of the first control signal ENVPPHV and the second control signal ENVDDHV after level shifting is comparatively high (7V˜0V) which is used to control the operation of the third and fourth p-type MOS transistors 20, 22 in the selecting switch module 18.
In the above-mentioned configuration, the power supply voltage switching circuit 10 can generate a power supply voltage VPS from the first voltage VPP and the second voltage VDD according to the control of the first control signal ENVPP and the second control signal ENVDD. If the first voltage VPP is chosen to be the power supply voltage VPS , the control circuit sets the first control signal ENVPP to a logic value of 0 (i.e. 0V) and the second control signal ENVDD to a logic value of 1 (i.e. 3V). After the level shift by the level shifting module 12, the first control signal ENVPP remains 0V but the second control signal ENVDD becomes 7V, and both are inputted to the selecting switch module 18. At the same time, the first voltage VPP is 7V and the second voltage VDD is 3V so the third p-type MOS transistor 20 is switched on and the fourth p-type MOS transistor 22 is switched off. As a result the power supply voltage VPS will output the value of the first voltage VPP (i.e. 7V). Oppositely if the second voltage VDD is chosen to be the power supply voltage VPS, the control circuit sets the first control signal ENVPP to a logic value of 1 (i.e. 3V) and the second control signal ENVDD to a logic value of 0 (i.e. 0V). After the level shift by the level shifting module 12, the first control signal ENVPP becomes 7V but the second control signal ENVDD remains 0V, and both are inputted to the selecting switch module 18. At the same time, the first voltage VPP is 7V and the second voltage VDD is 3V so the third p-type MOS transistor 20 is switched off and the fourth p-type MOS transistor 22 is switched on. As a result the power supply voltage VPS will output the value of the second voltage VDD (i.e. 3V).
Furthermore, the above operation takes into the assumption that the value of the first voltage VPP does not change. However in certain circuits, it is possible that the value of the first voltage VPP cannot always be maintained at a charge-pumped level, an example is the sharing of a pad between a charge-pumped voltage (such as VPP) and other signals. In this condition, the value of the first voltage VPP can be at a comparatively low level or even become 0V or floating in some situations. The level-shifters 14 and 16 of the level shifting module 12 use the first voltage VPP as the power supply voltage which renders the selecting switch module 18 unable to operate properly, or renders the third and fourth p-type MOS transistors 20 and 22 to be switched on at the same time causing the first voltage VPP and the second voltage VDD to short circuit which wastes energy.